View Z84C9008VEG_7525836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product specification z80 cmos microprocessors z84c90 kio serial/ parallel counter/timer ps011804-0612 copyright ?2012 zilog, inc. all rights reserved. www.zilog.com
ps011804-0612 life support policy z84c90 kio serial/parallel counter/timer product specification ii do not use this product in life support systems. life support policy zilog?s products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. a critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2012 zilog, inc all rights reserved . information in this publication con cerning the devices, applications, or technology described is intend ed to suggest possible uses and ma y be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of informati on, devices, or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. zmotion, z8 encore! xp and ez8 are trademarks or registered trademarks of zilog, inc. (an ixys company). all other product or service names ar e the property of their respective owners. warning:
ps011804-0612 revision history z84c90 kio serial/parallel counter/timer product specification iii revision history each instance in the following revision history table reflects a change to this document from its previous version. for more details, re fer to the corresponding pages or appropriate links provided in the table. date revision level description page number jun 2013 04 corrected to remove internal discussion tags. n/a jun 2012 03 updated to include missing information covered in the dc8321-00 databook (2q94). all sep 2002 02 added z84c90 kio peripheral: serial/parallel counter/ timer packages table, modified ac characteristics of the z84c90 table. 2 , 38 sep 2002 01 original issue. all
ps011804-0612 table of contents z84c90 kio serial/parallel counter/timer product specification iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 register address decoding for the kio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ctc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 sio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 kio command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 z84c90 kio: enhanced version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 precautions & limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9
ps011804-0612 list of figures z84c90 kio serial/parallel counter/timer product specification v list of figures figure 1. a block diagram of the z84c90 kio peripheral . . . . . . . . . . . . . . . . . . . . . 2 figure 2. z84c20 parallel input/output block diagram . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3. parallel interface adapter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. counter/timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. sio block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. z84c90 84-pin plcc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. 100-pin lqfp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. kio register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. pio interrupt vector word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. pio mode control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. pio i/o register control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. pio interrupt control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. pio mask control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15. pio interrupt disable word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16. ctc channel control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17. ctc time constant word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 18. ctc interrupt vector word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19. sio read register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. sio read register 1** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21. sio read register 2 (channel b only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 22. sio write register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 23. sio write register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 24. sio write register 2 (channel b only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 25. sio write register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 26. sio write register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 27. sio write register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 28. sio write register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ps011804-0612 list of figures z84c90 kio serial/parallel counter/timer product specification vi figure 29. sio write register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 30. pia control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 31. kio command register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 32. kio register 15: kio command register b . . . . . . . . . . . . . . . . . . . . . . . 28 figure 33. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 34. i/o read/write timing (m1 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 35. interrupt acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 36. counter/timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 37. reti timing standard function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 38. reti timing interrupt pending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 39. port i/o read/write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 40. serial i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 41. op code fetch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 42. internal daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ps011804-0612 list of tables z84c90 kio serial/parallel counter/timer product specification vii list of tables table 1. z84c90 kio peripheral: serial/para llel counter/timer packages . . . . . . . . 2 table 2. kio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. dc characteristics of the z84c90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 4. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5. ac characteristics of the z84c90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6. daisy chain parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7. daisy chain calculation data* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8. z84c90 kio ordering matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ps011804-0612 introduction z84c90 kio serial/parallel counter/timer product specification 1 introduction zilog?s z84c90 serial/parallel counter/timer kio is a multichannel, multipurpose i/o peripheral device designed to provide the end user with a cost-effective and powerful solu- tion to meet an assortment of peripherals requirements. the z84c90 kio peripheral com- bines the features of one z84c30 ctc, one z84c 20 pio and a z84c4x sio, plus an 8-bit, bit-programmable i/o port and a crystal osc illator into a single 84-pin plcc or 100-pin lqfp package. utilizing fifteen internal regist ers for data and programming information, the kio can easily be configured to any given system environment. although optimum performance is obtained with a z84c00 cpu, the kio can just as easily be used with any other cpu. features the z84c90 serial/parallel counter/timer kio offers the following features: ? two independent synchronous/asynchronous serial channels ? three 8-bit parallel ports ? four independent counter/timer channels ? on-chip clock oscillator/driver ? software/hardware resets ? designed in cmos for low power operations ? supports z80 family interrupt daisy chain ? programmable interrupt priorities ? 8, 10 and 12.5 mhz bus clock frequency ? single +5 v power supply ?
ps011804-0612 features z84c90 kio serial/parallel counter/timer product specification 2 figure 1 illustrates a block diagra m of the z84c90 kio peripheral. table 1. z84c90 kio peripheral: serial/parallel counter/timer packages part number package frequency (mhz) z84c9008asc 100-pin lqfp 8 z84c9010asc 100-pin lqfp 10 z84c9008vec 84-pin plcc 8 z84c9008vsc 84-pin plcc 8 z84c9010vsc 84-pin plcc 10 z84c9012vsc 84-pin plcc 12 figure 1. a block diagram of the z84c90 kio peripheral oscillator bus interface and control interrupt control pio pia/ mux sio ctc osc xtal1 xtal0 clkout d0?d7 a0?a3 cs mi rd iorq reset clk int ie1 ie0 pa0?pa7 ardy astb pb0?pb7 brdy bstb pc0?pcv rxda rxca txda txca ctsa dcda rxdb rxcb txdb txcb ctsb dcdb zc/to0 clk/trg0 zc/to1 clk/trg1 zc/to2 clk/trg2 zc/to3 clk/trg3 data bus control bus interrupt bus modem control
ps011804-0612 block descriptions z84c90 kio serial/parallel counter/timer product specification 3 block descriptions z84c20 parallel input/output logic unit. this logic unit provides both ttl- and cmos-compatible interfaces be tween peripheral devices and a cpu through the use of two 8-bit parallel ports. the cpu configures the logic to interface to a wide range of peripheral devices with no external logic. t ypical devices that are compatible with this interface are keyboards, printers and eprom/pal programmers. the parallel ports (designated port a and port b) are byte -wide and completely compati- ble with the z84c90 pio (see figure 2). these two ports feature several modes of opera- tion: input, output, bidirectional or bit cont rol. each port features two handshake signals (rdy and stb ) which can be used to control data transfers. the rdy (ready) indicates that the port is ready for data transfer while stb (strobe) is an input to the port that indi- cates when data transfer has occurred. each of the ports can also be programmed to inter- rupt the cpu upon the occurrence of specifi ed status conditions and generate unique interrupt vectors when the cpu responds. for more information about the operation of this portion of the logic, please refer to the z8420/z84c20 pio product specification (ps0180) . figure 2. z84c20 parallel input/output block diagram data control data or control handshake interrupt control lines peripheral interface internal control logic cpu bus i/o data or control handshake interrupt control port a i/o port b i/o internal bus 8 3
ps011804-0612 block descriptions z84c90 kio serial/parallel counter/timer product specification 4 parallel interface adap ter (pia) logic unit. this logic also offers an additional 8 bits of i/o to the user, referred to as the pia port (see figure 3). this port, designated as port c, is bit-programmable for data transfers; each bit can be individually programmed as either an input or an output. bit direction contro l is performed through the programming of the pia control register. when programmed as outputs, the output data latches are pro- grammed with an i/o write cycle; their state can be read with an i/o read cycle. when pro- grammed as inputs, the state of the external pin is read with the i/o read cycle. this port does not have handshake capabilities and offers no interrupt capabiliti es. this port is mul- tiplexed to provide the additional modem and cpu control signals fo r the serial i/o logic unit, when appropriate. when a read from the pia port occurs, input data will be latched when iorq , cs and rd all detected as active. the data bus will display this data as a result of the rising edge of the clock input after this occurrence. when a write to the pia port occurs, data will be written as a result of the rising edge of the clock input after iorq and cs have been detected as active and rd has been detected as inactive. counter/timer logic (ctc) unit. this logic unit provides the user with four individual 8-bit counter/timer channels that are compatib le with the z84c30 ctc (see figure 4). the counter/timers can be programmed by the cp u for a broad range of counting and timing applications. typical applications include ev ent counting, interrupt and interval timing and serial baud rate clock generation. each of the counter/timer channels, designated channels 0 through 3, have an 8-bit pres- caler (when used in timer mode) as well as its own 8-bit counte r to provide a wide range of count resolution. each of the channels also have their own clock/trigger input to quantify the counting process and an output to indi cate zero crossing/time-out conditions. with only one interrupt vector programmed into th is logic unit, each ch annel can generate a unique interrupt vector in response to the interrupt acknowledge cycle. figure 3. parallel interface adapter block diagram port c dir. ctrl. data bus pc0 ? pc7
ps011804-0612 block descriptions z84c90 kio serial/parallel counter/timer product specification 5 serial i/o logic unit. this logic unit provides the user wi th two separate serial i/o chan- nels that are completely compatible with th e z84c4x sio (see figure 5). their basic func- tions as serial-to-parallel and parallel-to-seria l converters can be programmed by a cpu for a broad range of serial communications ap plications. each channe l, designated chan- nel a and channel b, is capable of supporting all common asynchronous and synchronous protocols (monosync, bisync and sdlc/hdlc), byte- or bit-oriented. figure 4. counter/timer block diagram data control int ie1 ie0 zc/to clk/trg reset internal bus internal control logic interrupt logic counter/ timer logic 4 4 cpu bus i/o 8 6
ps011804-0612 block descriptions z84c90 kio serial/parallel counter/timer product specification 6 in the default state of the kio, each serial channel supports full duplex communication with separate transmit an d receive data lines, two modem control signals (cts and dcd ) and separate transmit and receive clock inputs. optionally, add itional modem and cpu/ dma control signals can be obtained through the pia port. for more information about the operation of this portion of the logic, please refer to the z8420/z84c20 pio product specification (ps0180) . figure 5. sio block diagram data control serial channel interrupt control lines i n t e r n a l b u s data clocks sync wait/ready modem or other control modem or other control serial channel data clocks sync wait /ready channel a control and status registers internal control logic cpu bus i/o interrupt control logic channel b control and status registers channel a channel b channel a control and status channel b control and status 8 7
ps011804-0612 block descriptions z84c90 kio serial/parallel counter/timer product specification 7 clock oscillator/driver logic unit. a clock oscillator/driver is available that will allow the user to eliminate circuitry with in a new design, or that can be used as another oscilla- tor within the system. this logic will accept either a cr ystal ceramic resonator or ttl- compatible clock input and generate a mos-comp atible clock output and also an oscillator reference output. zilog recommen ds a fundamental parallel reso nant crystal; see figure 6. the preferred value of the two capacitors c1 and c2 is 33 pf each. command logic unit. this logic unit provides for much more than just controlling the interface between the kio and the cpu. the ma in function provided by this unit is to allow the user to configure the internal inte rrupt daisy chain of the kio into a preferred sequence of peripherals to interrupt. any one of the three devices (sio, ctc, pio) can be the highest priority, while another can be se cond priority and the remaining device the third. the user can even configure the daisy chain such that no internal peripherals are involved in the chain. programming of the daisy chain configuration is performed by pro- gramming the command register with the ap propriate 3-bit pattern in addresses d0?d2, with d3 set to 1. a second function of this logic unit is to prov ide software-controllabl e hardware resets to each of the individual devices. as a result, an individual peripheral is allowed to be reset without having to reset the entire kio. requir ing bit d3 to be set to a 1 to program the daisy chain configuration allows the user to reset the individual devices without changing the daisy chain. the software reset commands for the individual devi ces still remain avail- able to the user. a third function of the command register allows the user to obtain use of the additional control signals of the sio logic instead of the pia port by programming bit d7 of the command register with a 1. figure 6. crystal connection ztali xtalo crystal inputs c1 c2
ps011804-0612 pin signals z84c90 kio serial/parallel counter/timer product specification 8 pin signals figure 7 shows the pin-outs for the 84-p in plcc z84c90 kio peripheral package; figure 8 shows the 100-pin lqfp pin-outs. figure 7. z84c90 84-pin plcc configuration 84-pin plcc clk/trg2 clk/trg1 clk/trg0 d7 d6 d5 d4 gnd v cc d3 d2 d1 d0 v cc xtal1 xtal0 gnd clock clkout osc int pc1 (syncb ) pc2 (dtrb ) pc3 (rtsb ) txda txca rxca rxda pa0 pa1 pa2 v cc pa3 gnd pa4 pa5 pa6 pa7 pc4 (rtsa ) pc5 (dtra ) pc6 (synca ) pc7 (wt/rdya ) 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 pco (wt /rdy gnd ctsa dcda dcdb ctsb txdb txcb rxcb rxdb a0 a1 a2 a3 cs m1 rd v cc iorq reset clk/trg3 gnd gnd pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 brdy bstb ardy astb zc/to3 zc/to2 zc/to1 zc/to 0 ie1 ie0 v cc
ps011804-0612 pin signals z84c90 kio serial/parallel counter/timer product specification 9 figure 8. 100-pin lqfp configuration 100-pin lqfp 1 5 10 15 20 25 26 30 35 40 45 50 51 55 60 65 70 75 76 80 85 90 95 100 nc nc gnd gnd pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 brdy bstb ardy astb zc/to3 zc/to2 zc/to1 zc/to0 ie1 ie0 v cc nc nc nc nc pc1 (syncb ) pc2 (dtrb ) pc3 (rtsb ) txda txca rxca rxda pa0 pa1 pa2 v cc pa3 gnd pa4 pa5 pa6 pa7 pc4 (rtsa) pc5 (dtra ) pc6 (synca ) pc7 (wt /rdya ) nc nc nc nc pc0 (wt /rdyb ) gnd csta dcda dcdb ctsb txdb txcb rxcb rxdb a0 a1 a2 a3 cs m1 rd v cc iorq reset clk/trg3 nc nc nc nc clk/trg2 clk/trg1 clk/trg0 d7 d6 d5 d4 gnd v cc d3 d2 d1 d0 v cc xtal1 xtal0 gnd clock clkout osc int nc nc
ps011804-0612 pin descriptions z84c90 kio serial/parallel counter/timer product specification 10 pin descriptions a0?a3. address bus (inputs). used to select the port/register for each bus cycle. ardy, brdy. port ready (outputs, active high). these signals indicate that the port is ready for a data transfer. in mode 0, the signal indicates that the port has data available to the peripheral device. in mode 1, the signal in dicates that the port is ready to accept data from the peripheral device. in mode 2, ardy indicates that port a has data available for the peripheral device, but that the data is not be placed onto pa0?pa7 until the astb sig- nal is active. brdy indicates that port a is able to accept data from a peripheral device. port b does not support mode 2 operation and can only be used in mode 3 when port a is programmed for mode 2. brdy is not associa ted with port b when it is operating in mode 3. astb , bstb . port strobe (inputs, active low). these signals indicate that the peripheral device has performed a transfer. in mode 0, th e signal indicates that the peripheral device has accepted the data present on the port pins. in mode 1, the signal causes the data on the port pins to be latched onto port a. in mode 2, astb low causes the data in the output data latch of port a to be pl aced onto the port a pins. bstb low causes the data present on the port a pins to be latched into the po rt a input data latch. the end of the current transaction is noted by the rising edge of these signals. port b does not support mode 2 operation, and can only be used in mode 3 when port a is programmed for mode 2. bstb is not associated with port b when it is operating in mode 3. clk/trg0?clk/trg3. external clock/timer trigger (inputs, user-selectable active high or low). these four pins correspond to the four counter/timer channels of the kio. in counter mode, each active edge causes the downcounter to decrement. in timer mode, an active edge starts the timer. clkout. clock out (output). this output is a divide-by-two of the oscillator (xtal) input. clock. system clock (input). this clock must be the same as (or a derivative of) the cpu clock. if the clkout is to be used as th e system clock, then these two pins must be connected together. note: note:
ps011804-0612 pin descriptions z84c90 kio serial/parallel counter/timer product specification 11 cs. chip select (input, active low). used to ac tivate the internal register decoding mech- anism and allow the kio to perform a data transfer to/from the cpu. ctsa , ctsb . clear to send (inputs, active low). these signals are modem control sig- nals for the serial channels. when programm ed for auto enable, a low on these pins enables their respective transm itters. if not programmed as auto enable, these pins may be used as general-purpose input signals. d0?d7. data bus (bidirectional, ac tive high, tristated). used for data exchanges between the cpu and the kio for programming and data transfer. the kio also monitors the data bus for return from interrupt (r eti) instructions to maintain its interrupt under service (ius) status. dcda , dcdb . data carrier detect (inputs, active low). these signals are modem control signals for the serial channels. when progr ammed for auto enable, a low on these pins enables their respective receivers. if not prog rammed as auto enable, these pins may be used as general-purpose input signals. dtra , dtrb . data terminal ready (o utputs, active low). these signals are modem con- trol signals for the serial channels. they follo w the state programmed into their respective serial channels, and are multiplexed with port c, bits 5 and 2, respectively. iei. interrupt enable in (input, active high). this signal is used with interrupt enable out (ieo) to form a priority daisy chain when th ere is more than one interrupt-driven device. a high on this line indicates that no higher-priority device is requesting an interrupt. ieo. interrupt enable out (output, active high). th is signal is used with interrupt enable in (iei) to form a priority daisy chain when th ere is more than one interrupt-driven device. a high on this line indicates that this device is requesting an interrupt, and that no higher- priority device, is not requesting an interru pt. a low blocks any lower-priority devices from requesting an interrupt. iorq. input/output request (input, active low). iorq is used with rd , a0?a3, and cs to transfer data between th e kio and the cpu. when iorq , rd , and cs are active low, the device selected by a0?a3 transfers data to the cpu. when iorq and cs are active low, but rd is active high, the device selected by a0?a3 is written into by the cpu. when iorq and m1 are both active low, the kio may respond with an interrupt vector from its highest-priority interrupting device. m1. machine cycle 1 (input, active low). when m1 and rd are low, the z80 cpu fetches an instruction from memory; the kio decodes this cycl e to determine if the reti instruction sequence is being executed. when m1 and iorq are both active, the kio decodes the cycle to be an in terrupt acknowledge, and may respond with a vector from its highest-priority interrupting device.
ps011804-0612 pin descriptions z84c90 kio serial/parallel counter/timer product specification 12 osc. oscillator (output). this output is a reference clock for the oscillator. pa0?pa7. port a bus (bidirectional, tristated). one of the 8-bit ports of the pio. pa0 is the least-significant bit of the bus. pb0?pb7. port b bus (bidirectional, tristated). one of the 8-bit ports of the pio. pb 0 is the least-significant bit of the bus. this port can also supply 1.5ma at 1.5v to drive dar- lington transistors. pc0?pc7. port c bus (bidirectional, tristated). pc 0 is the least-significant bit of the bus. these pins are multiplexed between the 8-bi t pia and additional modem control signals for the serial channels. rd. read (input, active low). when rd is active, a memory or i/o read operation is in progress. rd is used with a0?a3, cs and iorq to transfer data between the kio and cpu. reset. reset (input, active low). a low on this pin forces the kio into a reset condi- tion. this signal must be active for a mini mum of three clock cycles. when the kio is reset, the following events occur: ? the pio ports are in mode 1 operation ? handshakes are inactive and interrupts are disabled ? the pia port is in input mode and active ? ctc channel counting is terminat ed and interrupts are disabled ? sio channels are disabled ? marking with interrupts is disabled ? all control registers must be rewritten after a hardware reset. rtsa , rtsb . request to send (outputs, active lo w). these signals are modem control signals for their serial channels. they follo w the inverse state pr ogrammed into their respective serial channels, and are multiplexed with port c, bits 4 and 3, respectively. rxca , rxcb . receive clock (inputs, active low). th ese clocks are used to assemble the data in the receiver shift regi ster for their serial channels. data is sampled on the rising edge of the clock. rxda, rxdb. receive data (inputs, active high). the se pins are the input data pins to the receive shift register for their serial channels. synca , syncb . synchronization (bidirectional, activ e low). in the asynchronous mode of operation, these pins act much like the cts and dcd pins. transitions affect the sync/
ps011804-0612 register address decoding for the kio z84c90 kio serial/parallel counter/timer product specification 13 hunt status bit for their respective serial chan nels, but serve no other purpose. these pins are multiplexed with port c, bits 6 and 1, respectively. txca , txcb . transmit clock (inputs, active low). th ese clocks are used to transmit data from the transmit shift register for their serial channels. data is tr ansmitted on the falling edge of the clock. txda, txdb. transmit data (outputs, active high). th ese pins are the output data pins from the transmitter for their serial channels. wt /rdya , wt /rdyb . wait/ready (outputs, open-drain when programmed as wait; tristated when programmed as ready). these pins may be programmed as ready lines for a dma controller or wait lines for interfacing to a cpu. as a ready line, these pins indi- cate (when active low) that the transmitter or the receiver requests a transfer between the serial channel and the dma. as a wait line, these pins dictate (when low) that the cpu must wait until the transmitter or receiver can complete the requested transaction. these pins are multiplexed with port c, bit 7 and 0, respectively. xtali. crystal/clock connection. (input). xtalo. crystal connection. (output). zc/to0?zc/to3. zero count/time-out (outputs, active high). these four pins are out- puts from the four counter/timer channels of the kio. each pin pulses high when its cor- responding downcounter reaches 0. register address decoding for the kio address lines a0?a3 determine which one of the 16 control registers is being accessed. table 2 shows the address decoding of each of the kio control registers; also see figure 9 on page 15. table 2. kio registers address a3a2a1a0 register 0: pio port a data 0000 register 1: pio port a command 0001 register 2: pio port b data 0010 register 3: pio port b command 0011 register 4: ctc channel 0 0100 note: additionally, iorq and cs must be low. registers are written to or read from by the cpu, applying a 1 or a 0 respectively on the rd pin.
ps011804-0612 register address decoding for the kio z84c90 kio serial/parallel counter/timer product specification 14 register 5: ctc channel 1 0101 register 6: ctc channel 2 0110 register 7: ctc channel 3 0111 register 8: sio port a data 1000 register 9: sio port a command/status 1001 register 10: sio channel b data 1010 register 11: sio channel b command/status1011 register 12: pia port c data 1100 register 13: pia port c command 1101 register 14: kio command 1110 register 15: kio command b 1111 table 2. kio registers (continued) address a3a2a1a0 note: additionally, iorq and cs must be low. registers are written to or read from by the cpu, applying a 1 or a 0 respectively on the rd pin.
ps011804-0612 register address decoding for the kio z84c90 kio serial/parallel counter/timer product specification 15 figure 9. kio register addressing
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 16 register programming this section describes how the bits within each of the z84c90 kio?s command registers change their respective comman d register functions, as well as the effects of such changes. pio registers the pio registers described in this section ap ply to channels a and b (additionally, see the register address decoding for the kio section on page 13). for more information about these pio registers, please consult the z80 cpu peripherals user manual (um0081) . interrupt vector word. when bit 0 of the command register is cleared to 0, the command register functions as the interru pt vector word register. the pio logic unit is designed to work with the z80 cpu in inte rrupt mode 2. this word must be programmed if interrupts are to be used; bit d0 must be 0. see figure 10. mode control word. when bits b2 to b0 are set to 1, the command register functions as the mode control word register . selects the port operating mo de. this word is required and can be written at a ny time. see figure 11. figure 10. pio interrupt vector word register figure 11. pio mode control word register v7 v6 v5 v4 v3 v2 v1 v0 identifies interrupt vector user-supplied interrupt vector d7 d6 d5 d4 1 1 1 1 dont care mode select 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 identifies mode control word
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 17 i/o register control word. when mode 3 is selected, the mode control word data must be followed by the loading of the i/o register control word data. th is word configures the i/o register, which defines which port lines are inputs or outputs. a 1 indicates input, while a 0 indicates output. this word is re quired with in mode 3. see figure 12. pio interrupt control word. when bits d3 to d0 are loaded with 0111, the command register functions as the pio interrupt contro l word register. in mode 3 operation, hand- shake signals are not used. interrupts are genera ted as a logic function of the input signal levels. the interrupt control wo rd sets the logic conditions an d the logic levels required for generating an interrupt. two logic conditions or functions are available: and (if all input bits change to the active level, an interrupt is triggere d) and or (if any one of the input bits change to th e active logic level, an interrupt is triggered). the user can also pro- gram which input bits are to be considered as part of this logic func tion. bit d6 sets the logic function, bit d5 sets the logic level and bit d4 specifies the mask control word data to follow. see figure 13. mask control word. this words sets the mask contro l register, thus allowing any unused bits to be masked off. if any bits are to be masked, bit d4 of the interrupt control figure 12. pio i/o register control word notes: 1. regardless of the operating mode, setting bit d4 = 1 causes any pending interrupts to be cleared. 2. the port interrupt is not enabled until the interrupt function enable is followed by an active m1 . figure 13. pio inte rrupt control word i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 0: sets bit to output 1: sets bit to input 1 h/l 0111 d7 d0 identifies interrupt control word 1 = mask follows 1 = active high 1 = and function 1 = interrupt function enable 2 1
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 18 word must be set. when bit d4 of the interrupt control wo rd is set, the next word loaded into the command register must be the mask control word. to mask an input bit, the cor- responding mask control word bit must be a 1. see figure 14. interrupt disable word. when bits b3 to b0 are loaded with 0011, the command register functions as the interrupt disable word register. this word can be used to enable or dis- able a port?s interrupts without change the remainder of the port?s interrupt conditions. see figure 15. ctc registers the ctc registers apply to channels 0, 1, 2 an d 3 (additionally, see the register address decoding for the kio section on page 13). for more in formation about these ctc regis- ters, please consult the z80 cpu peripherals user manual (um0081) . channel control word. this word sets the operating mo des and parameters as described in the following paragraphs. bit d0 of the ctc register must be a 1 to indicate a control word; otherwise, it is an interru pt vector word. see figure 16. figure 14. pio mask control word figure 15. pio interrupt disable word d7 d5 d3 d2 d1 d6 d4 d0 mb0-mb7 mask bits a bit is monitored for an interrupt if it is defined as an input and the mask bit is set to 0. d7 d5d6 d4 0 0 1 1 identifies interrupt disable word 1 = dont care 0 = interrupt disable 1 = interrupt enable
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 19 interrupt enable. bit d7 enables the interrupt logic so that an interrupt output (int ) can be generated at zero count. interrupts can be programmed in either mode and can be enabled or disabled at any time. mode. bit d6 selects either time r mode or counter mode. prescale factor. bit d5 selected the prescale factor for use in timer mode. either divide- by-16 or divide-by-256 is available. clock/trigger edge selector. bit d4 selects the active edge of the clk/trg input pulses. timer trigger. bit d3 selects the trigger mode for timer operation. either an automatic or an external trigger can be selected. time constant. bit d2 indicates that the next word lo aded into this register is the time constant data for the downcounter. software reset. setting bit d1 indicates a software reset operation. ? time constant word. before a channel can start counting, it must receive a time constant word. the time constant value can be anywhe re between 1 and 256, with 0 being accepted as a count of 256. see figure 17. figure 16. ctc channel control word d7 d5d6 d4 0 0 1 1 control or vector 0 = vector 1 = control word reset 0 = continued operation 1 = software reset time constant 0 = no time constant follows 1 = time constant follows timer trigger* 0 = automatic trigger when time constant is loaded 1 = clk/trg pulse starts timer interrupt 1 = enable interrupt 0 = disables interrupt mode 0 = selects timer mode 1 = selects counter mode prescaler value* 0 = value of 16 1 = value of 256 clk/trg edge selection 0 = selects falling edge 1 = selects rising edge
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 20 interrupt vector word. if one or more of the ctc channels have interrupts enabled, the interrupt vector word must be programmed into the ctc register. only the five most significant bits of this word are programmed, and bit d0 must be 0. bits d2?d1 are auto- matically modified by the ct c channel when it responds with an interrupt vector. see figure 18. sio registers these registers apply to channe ls a and b (additionally, see the register address decod- ing for the kio section on page 13). the command/stat us register initially functions as write register 0 (wr0) and operates as a pointe r to the read registers or to the write regis- ters. the read register for write register 0 is rr0. the read registers for write register 1 and write register 2 are rr1 and rr2, respectively. for more information about these sio registers, please consult the z80 cpu peripherals user manual (um0081) . figure 17. ctc time constant word figure 18. ctc interrupt vector word d7 d5d6 d4 d3 d2 d1 d0 tc0 tc1 tc2 tc3 tc7 tc6 tc5 tc4 d7 d5d6 d4 d3 d2 d1 d0 0 = interrupt vector word 1 = control word channel identifier (automatically inserted by ctc) 0 0 = channel 0 0 1 = channel 1 1 0 = channel 2 1 1 = channel 3 supplied by user
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 21 read registers. sio channel b contains three read registers while channel a contains only two that can be read to obtain status in formation. to read the contents of a register (other than rr0), the program must first write a pointer to wr0 in exactly the same man- ner as a write register operation. the next i/o read cycle will place the contents of the selected read register onto the data bus. see figures 19 through 21. note: *used with external/status interrupt modes. figure 19. sio read register 0 notes: *residue data for eight rx bits/character programmed. **used with a special receive condition mode. figure 20. sio read register 1** d7 d5d6 d4 d3 d2 d1 d0 rx character available interrupt pending (ch. a only) tx buffer empty dcd break/abort tx underrun/eom cts sync/hunt * d7 d5d6 d4 d3 d2 d1 d0 all sent field bits in previous byte field bits in second previous byte 100 0 3 010 0 4 110 0 5 001 0 6 101 0 7 011 0 8 111 1 8 000 2 8 end of frame (sdlc) crc/framing error rx overrun error parity error *
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 22 write registers. sio channel b contains eight write registers while channel a contains only seven that are programmed to configur e the operating modes and characteristics of each channel. with the exception of wr0, prog ramming the write registers is a two-step operation. the first operation is a pointer written to wr0 that points to the selected regis- ter. the second operation is the actual control wo rd data that is written into the register to configure the sio channel. see figures 22 thro ugh 29 to examine the details of these write registers. note: *variable if status affects vector is also programmed. figure 21. sio read register 2 (channel b only) d7 d5d6 d4 d3 d2 d1 d0 v0 v1* v2* v3* v7 v6 v5 v4 interrupt vector
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 23 figure 22. sio write register 0 note: *or on special condition. figure 23. sio write register 1 d7 d5d6 d4 d3 d2 d1 d0 1 00 0 10 1 10 0 01 1 01 0 11 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 00 0 0 0 1 1 1 1 0 register 0 register 1 register 2 register 3 register 4 register 5 register 6 register 7 null code send abort (sdlc) reset ext/status interrupts channel reset enable interrupt on next rx character reset txint pending error reset return from interrupt (channel a only) reset rx crc checker null code 0 0 1 0 reset tx crc generator 10 reset tx underrun/eom latch 11 d7 d5d6 d4 d3 d2 d1 d0 0 1 0 1 0 0 1 1 external interrupt enable tx interrupt enable status affects vector (channel b only) rx interrupt disable rx interrupt on first character interrupt on all rx characters (parity affects vector) interrupt on all rx characters (parity does not affect vector) wait/ready function wait/ready on r/t wait/ready enable *
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 24 figure 24. sio write register 2 (channel b only) figure 25. sio write register 3 d7 d5d6 d4 d3 d2 d1 d0 v0 v1 v2 v3 v7 v6 v5 v4 interrupt vector d7 d5d6 d4 d3 d2 d1 d0 rx enable sync character load inhibit address search mode (sdlc) rx crc enable 0 0 1 0 10 11 rx 7 bits/character rx 5 bits/character rx 6 bits/character rx 8 bits/character auto enables enter hunt phase
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 25 figure 26. sio write register 4 figure 27. sio write register 5 d7 d5d6 d4 d3 d2 d1 d0 parity enable parity even/odd 0 0 1 0 10 11 x16 clock mode x1 clock mode x32 clock mode x64 clock mode 0 0 1 0 10 11 16-bit sync character 8-bit sync character sdlc mode (01111110 flag) external sync mode 0 0 1 0 10 11 1 stop bit/character sync modes enable 1? stop bits/character 2 stop bits/character d7 d5d6 d4 d3 d2 d1 d0 tx crc enable rts sdlc/crc-18 tx enable send break dtr 0 0 1 0 10 11 tx 7 bits per character tx 5 bits or less per character tx 6 bits per character tx 8 bits per character
ps011804-0612 register programming z84c90 kio serial/parallel counter/timer product specification 26 pia registers the pia port can be configured for any combination of input and output bits. the direc- tion is controlled by writing to the pia contro l register. a 1 written to a bit position indi- cates that the respective bit shou ld be an input (see figure 30 ). all bits are inputs upon reset. note: *also sdlc address field. figure 28. sio write register 6 note: for sdlc, these bits must be programmed to 01111110 for flag recognition. figure 29. sio write register 7 d7 d5d6 d4 d3 d2 d1 d0 sync bit 0 sync bit 1 sync bit 2 sync bit 3 sync bit 7 sync bit 6 sync bit 5 sync bit 4 * d7 d5d6 d4 d3 d2 d1 d0 sync bit 8 sync bit 9 sync bit 10 sync bit 11 sync bit 15 sync bit 14 sync bit 13 sync bit 12 *
ps011804-0612 z84c90 kio: enhanced version z84c90 kio serial/parallel counter/timer product specification 27 kio command register command register a is used to program soft ware resets and to configure the internal interrupt daisy chain priority (see figure 31). this register should be programmed before all others. the reset control bits are momentary; writing a 1 pulses an internal reset signal to the appropriate device. z84c90 kio: enhanced version a subsequent revision of the z84c90 mcu features an enhancement which allows users to simulate the return from interrupt sequ ence with software. this feature allows the interfacing of the cpu to other devices in addition to the z80 cpu (or the z180/z280). figure 30. pia control register figure 31. kio command register a i/o7 i/o5 i/o3 i/o2 i/o1 i/o6 i/o4 i/o0 0 = sets bit to output 1 = sets bit to input d7 d5d6 d4 d3 d2 d1 d0 001 000 010 011 sio, ctc, pio none daisy chain configuration daisy chain write enable reset pio reset ctc reset sio sio/pia mux 0 = pia 1 = sio sio, pio, ctc ctc, sio, pio 100 101 110 ctc, pio, sio pio, sio, ctc pio, sio, ctc 111 none
ps011804-0612 z84c90 kio: enhanced version z84c90 kio serial/parallel counter/timer product specification 28 command register b. writing a 1 to a particular command bit location of the kio gen- erates a reti sequence internally. every time a reti is required, a 1 is written to this bit to allow software control of the reti. programming of this feature. this revision has one newly assigned register at register address 15 (this location is reserved on the original version). the bit assignments for this register are shown in figure 32. writing a 1 to the bit d0 location of this re gister enables the kio to simulate a reti sequence. writing a 0 to this bit yields no eff ect. the upper 7 bits of this register (d7?d1) are reserved and should be programmed to 0. if this register is read, unpredictable data is returned. after writing a 1 to this bit, 8 clock cycles of access recovery time is required before addi- tional access to the kio can o ccur. if accessing the kio within this recovery period, the kio ignores the transaction on the bus. ? ? when simulating reti, the status of the iei pin is ignored with an internally forced h. if there are other peripherals on the upper interru pt daisy chain, caution must be exercised. figure 32. kio register 15: kio command register b d7 d6 d5 d4 d3 d2 d1 d0 software reti (write only) reserved notes:
ps011804-0612 electrical characteristics z84c90 kio serial/parallel counter/timer product specification 29 electrical characteristics the data in this chapter represents all known data prior to qualifi cation and characteriza- tion of the z84c90 kio device and is theref ore subject to change. additional electrical characteristics can be found in the in dividual chapters of this document. absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this rating is a stress rating only. operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. standard test conditions the dc characteristics and capacitance sections that fo llow apply to the following stan- dard test conditions, unless otherwise noted. all voltages are refe renced to gnd (0v). positive current flows into the referenced pin. available operating temperature ranges are: ? s = 0c to +70c ? e = ?40c to +100c ? voltage supply range: +5.0v 10% all ac parameters assume a load capacitance of 100 pf, as shown in figure 33. add a 10 ns delay for each 50 pf increase in load up to a maximum of 200 pf for the data bus and 100 pf for the address and control lines. ac timing measurements are referenced to 1.5 volts (except for clock, which is re ferenced to the 10% and 90% points. voltage on v cc with respect to v ss ?0.3v to +7.0v voltages on all inputs with respect to v ss ?0.3v to v cc +0.3v operating ambient temperature see ordering information storage temperature ?65c to +150c
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 30 dc characteristics table 3 lists the direct current characteristics for the z84c90 kio periph eral. in this table, v cc = 5.0 v 10% unless otherwise specified. figure 33. test load diagram table 3. dc characteristics of the z84c90 symbol item min max unit condition v ilc clock input low voltage ?0.3 +0.45 v v ihc clock input high voltage v cc ? 0.6 v cc + 0.3 v v il input low voltage ?0.3 +0.8 v v ih input high voltage 2.2 v cc v v ol output low voltage +0.4 v i ol = 2.0ma v oh1 output high voltage 1 2.4 v i oh = ?1.6ma v oh2 output high voltage 2 v cc ? 0.8 v i oh = ?250ma i li input leakage current 10.0 a v in = 0.4~v cc i ol 3-state leakage current 10.0 a v in = 0.4~v cc i l(sy) sync pin leakage current ?40 +10 a v in = 0.4~v cc note: *measurement made with output floating over specified temper ature and voltage ranges with v cc = 5 v, v ih = v cc ? 0.2 v and v il = 0.2 v. 250 from output under test ? a 100 pf +5v 2.1k
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 31 figure 34 shows the timing of reads and wr ites for the z84c90 kio peripheral?s i/o block. i ohd darlington drive current ? (port b and zc/t00~3) ?1.5 ma v oh = 1.5 v ? r ext = 390 ? i cc power supply current* 8 mhz 15 ma 10 mhz 15 ma 12.5 mhz 15 ma figure 34. i/o read/write timing (m1 = 1) table 3. dc characteristics of the z84c90 (continued) symbol item min max unit condition note: *measurement made with output floating over specified temper ature and voltage ranges with v cc = 5 v, v ih = v cc ? 0.2 v and v il = 0.2 v. 1 2 3 4 5 6 7 8 9 10 11 15 10 8 12 7 6 47 48 48 49 clock a0Ca3 cs iorq rd d0Cd7 rd wt/rdy wait mode wt/rdy ready mode read cycle write cycle d0Cd7
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 32 figure 35 shows the timing of the z84c90 kio peripheral?s interrupts. figure 36 shows the timing of the z84c90 kio peripheral?s counter/timer. figure 35. interrupt acknowledge cycle figure 36. counter/timer timing 36 18 14 16 19 11 7 13 17 clock int m1 iorq d0?d7 ie1 ie0 t2 twa* twa* t3 t4 t1 *wait state. 37 38 39 40 41 42 43 44 45 46 36 clock clk/trg counter clk/trg timer zc/to int
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 33 figure 37 shows the timing for the reti sequence. figure 38 shows the interrupt timing that occurs when a reti sequence is pending. figure 37. reti timing standard function t4 t1 t2 t3 t4 t1 ed op code fetch 1 4d op code fetch 2 t2 t3 t4 t1 22 71 73 12 74 74 clock m1 rd data iei ieo
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 34 figure 39 shows the read and write timing of the z84c90 kio peripheral?s gpio ports. figure 38. reti timing interrupt pending t4 clock m1 rd data iei ieo t1 t2 t3 t4 t1 ed op code fetch 1 4d op code fetch 2 t2 t3 t4 t1 22 71 72 73 12 74 74
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 35 figure 40 shows the serial timing of the z84c90 kio peripheral?s i/o block. figure 39. port i/o read/write timing clock iorq rd port c input port c output rdy stb mode 0 mode 1 mode 2 mode 3 int 34 35 23 24 25 29 26 28 30 27 8 32 31 33
ps011804-0612 dc characteristics z84c90 kio serial/parallel counter/timer product specification 36 figure 41 shows the z84c90 kio peripheral operation code fetch timing. figure 40. serial i/o timing cts dcd sync txc txd wt/rdy rxc rxd sync wt/rdy int int 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 70
ps011804-0612 capacitance z84c90 kio serial/parallel counter/timer product specification 37 capacitance table 4 lists the clock and input/output capa citance values for the z84c90 kio periph- eral. ac characteristics table 5 lists the alternati ng current characteristics for the z84c90 kio peripheral. figure 41. op code fetch cycle table 4. capacitance symbol parameter minimum maximum unit c clock clock capacitance 10 cf ci n input capacitance 10 cf c out output capacitance 15 cf note: t a = 25c, f = 1 mhz. clock m1 rd d 0 ?d 7 ie1 ie0 72 71 17 16 12 21 20 73 73 22 74 74
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 38 table 5. ac characteristics of the z84c90 no. symbol parameter 8 mhz 10 mhz 1,6 12.5 mhz 1,6 u/m min max min max min max bus interface timing 1 tcc clock cycle time 125 dc 100 dc 80 dc ns 2 twch clock pulse width (high) 55 dc 42 dc 32 dc ns 3 twcl clock pulse width (low) 55 dc 42 dc 32 dc ns 4 tfc clock fall time 10 10 10 ns 5 trc clock rise time 10 10 10 ns 6 tsa(rlf) address, cs setup to rd , iorq fall 50 40 30 ns 7 tsrl(cr) rd , iorq to clock ? rise setup505040ns 8 th hold time for specified setup 15 15 15 ns 9 tdcr(do) clock rise to data out delay 100 80 65 ns 10 tdrlr(doz) rd , iorq rise to data out float delay 75 60 55 ns 11 thrdr(d) m1 ,rd ,iorq rise to data float 15 15 15 ns 12 tsd(cr) data in to clock rise setup 30 25 22 ns 13 tdioi(doi) iorq fall to data out delay ? (intack cycle) 2 95 95 95 ns 14 thior(d) iorq rise to data float (intack) 15 15 15 ns 15 thior(a) iorq rise to address hold 15 15 15 ns 16 tsm1f(cr) m1 fall to clock rise setup 40 40 40 ns 17 tsm1r(cf) m1 rise to clock fall setup ? (m1 cycle) ?15 ?15 ?15 ns 18 tdm1f(ieof) m1 fall to ieo fall delay (interrupt immediately preceding m1 fall) 3 ???n s 19 tsiei(iof) iei to iorq fall setup 3 ns notes: 1. maximum sio data rate is f clock by 5, in which f clock = 1 t c c. 2. for a z80 cpu operating above 8 mhz, one wait state is required to meet this parameter. 3. these daisy chain parameters include contributions fr om the pio, sio and ctc cells, and vary slightly depending on how they are ordere d by the kio command register. 4. counter mode only; when using a cycle time less than 3 tcc, parameter #37 must be met. 5. units are tcc. 6. if the cpu is a z80 cpu and if it is required to have mu ltiple z80 peripherals in the system, then the time period between m1 to iorq must be extended. 7. any open-drain output must add a re gister-capacitor (rc) time cons tant to the specification value.
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 39 bus interface timing (continued) 20 tdieif(ieof) iei fall to ieo fall delay 3 160 150 125 ns 21 tdieif(ieor) iei rise to ieo rise delay ? (after ed decode) 3 160 150 125 ns 22 tsiei(cf) iei to clock fall setup (for 4d decode) 50 40 30 ns 23 tsior(cf) iorq rise to clock fall setup ? (to activate rdy on next clock) 100 100 100 ns pio timing 24 tdcf(rdyr) clock fall to rdy rise delay 100 100 100 ns 25 tdcf(rdyf) clock ? fall to rdy ? fall delay 100 100 ns 26 twstb stb pulse width 100 80 60 ns 27 tsstbr(cf) stb ? rise to clock ? fall setup ? (to activate rdy on next clock cycle) 100 100 ns 28 tdiof(pd) iorq ? fall to port data valid ? (mode 0) 140 120 110 ns 29 tspd(stbr) port a,b data to stb rise setup time (mode 1) 140 75 75 ns 30 tdstbi(pd) stb fall to port a,b data valid delay (mode 2) 150 120 110 ns 31 tdstbr(pdz) stb rise to port data float delay (mode 2) 140 120 110 ns 32 tdpd(intf) port data match to int fall delay (mode 3) 250 200 160 ns 33 tdstbr(intf) stb rise to int fall delay 290 220 190 ns 34 tspd(rif) pia port data to rd , iorq fall setup tbd tbd tbd ? table 5. ac characteristics of the z84c90 (continued) no. symbol parameter 8 mhz 10 mhz 1,6 12.5 mhz 1,6 u/m min max min max min max notes: 1. maximum sio data rate is f clock by 5, in which f clock = 1 t c c. 2. for a z80 cpu operating above 8 mhz, one wait state is required to meet this parameter. 3. these daisy chain parameters include contributions fr om the pio, sio and ctc cells, and vary slightly depending on how they are ordere d by the kio command register. 4. counter mode only; when using a cycle time less than 3 tcc, parameter #37 must be met. 5. units are tcc. 6. if the cpu is a z80 cpu and if it is required to have mu ltiple z80 peripherals in the system, then the time period between m1 to iorq must be extended. 7. any open-drain output must add a re gister-capacitor (rc) time cons tant to the specification value.
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 40 pio timing (continued) 35 tdcr(pd) clock rise to port data valid delay 80 80 80 ns ctc timing 36 tdcr(intf) clock rise to int rise delay tcc+100 tcc+80 tcc+75 ns 37 tsctrr(cr)c clk/trg rise to clock rise setup (for immediate count, counter mode) 90 90 75 ns 38 tsctrr(cr)t clk/trg rise to clock rise setup (for enabling prescaler on following clock ? rise, timer mode) 90 90 75 ns 39 tdctrr(intf) clk/trg ri se to int fall delay tsctrr(cr) satisfied tsctrr(cr) not satisfied (36)+(38) (1)+(36)+(38) (36)+(38) (1)+(36)+(38) (36)+(38) (1)+(36)+(38) ns 40 tcctr clk/trg cycle time 4 (2tcc) dc (2tcc) dc (2tcc) dc ns 41 twctrh clk/trg width high 90 dc 90 dc 75 dc ns 42 twctri clk/trg width low 90 dc 90 dc 75 dc ns 43 trctr clk/trg rise time 30 30 30 ns 44 tfctr clk/trg fall time 30 30 30 ns 45 tdcr(zcr) clock rise to zc/to rise delay 80 80 80 ns 46 tdcf(zcf) clock fall to zc/to fall delay 80 80 80 ns sio timing 47 tdiof(w/rf) iorq fall to wt /rdy fall delay (wait mode) 130 110 110 ns 48 tdcr(w/rf) clock rise to wt /rdy delay ? (ready mode) 85 85 85 ns 49 tdcf(w/rz) clock fall to wt /rdy float delay (wait mode) 7 90+rc 80+rc 75+rc ns table 5. ac characteristics of the z84c90 (continued) no. symbol parameter 8 mhz 10 mhz 1,6 12.5 mhz 1,6 u/m min max min max min max notes: 1. maximum sio data rate is f clock by 5, in which f clock = 1 t c c. 2. for a z80 cpu operating above 8 mhz, one wait state is required to meet this parameter. 3. these daisy chain parameters include contributions fr om the pio, sio and ctc cells, and vary slightly depending on how they are ordere d by the kio command register. 4. counter mode only; when using a cycle time less than 3 tcc, parameter #37 must be met. 5. units are tcc. 6. if the cpu is a z80 cpu and if it is required to have mu ltiple z80 peripherals in the system, then the time period between m1 to iorq must be extended. 7. any open-drain output must add a re gister-capacitor (rc) time cons tant to the specification value.
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 41 sio timing (continued) 50 twph pulse width high 150 120 100 ns 51 twpi pulse width low 150 120 100 ns 52 tctxc txc cycle time 250 dc 200 dc 160 dc ns 53 twtxch txc width high 85dc80dc70dcns 54 twtxcl txc width low 85 dc 80 dc 70 dc ns 55 trtxc txc rise time 60 60 60 ns 56 tftxc txc fall time 60 60 60 ns 57 tdtxcf(txd) txc fall to txd delay (x1 mode) 160 120 115 ns 58 tdtxcf(w/rf) txc fall to wt /rdy fall delay ? (ready mode) 5 5959 59ns 59 tdtxcf(intf) txc fall to int fall delay 5 5959 59ns 60 tcrxc rxc cycle time 250 dc 200 dc 160 dc ns 61 twrxch rxc width high 85dc80dc70dcns 62 twrxcl rxc width low 85 dc 80 dc 70 dc ns 63 trrxc rxc rise time 60 60 60 ns 64 tfrxc rxc fall time 60 60 60 ns 65 tsrxd(rxcr) rxd to rxc rise setup 0 0 0 ns 66 thrxcr(rxd) rxc rise to rxd hold time 80 60 50 ns 67 tdrxcr(w/rf) rxc rise to w /rdy fall delay (ready mode) 5 10 13 10 13 10 13 ns 68 tdrxcf(intf) rxc to int fall delay 5 10 13 10 13 10 13 ns 69 tdrxcr ? (syncf) rxc rise to sync fall delay (output mode) 474747ns table 5. ac characteristics of the z84c90 (continued) no. symbol parameter 8 mhz 10 mhz 1,6 12.5 mhz 1,6 u/m min max min max min max notes: 1. maximum sio data rate is f clock by 5, in which f clock = 1 t c c. 2. for a z80 cpu operating above 8 mhz, one wait state is required to meet this parameter. 3. these daisy chain parameters include contributions fr om the pio, sio and ctc cells, and vary slightly depending on how they are ordere d by the kio command register. 4. counter mode only; when using a cycle time less than 3 tcc, parameter #37 must be met. 5. units are tcc. 6. if the cpu is a z80 cpu and if it is required to have mu ltiple z80 peripherals in the system, then the time period between m1 to iorq must be extended. 7. any open-drain output must add a re gister-capacitor (rc) time cons tant to the specification value.
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 42 figure 42 offers a visual representation of th e daisy chain sequence; table 6 lists 8 mhz, 10 mhz and 12 mhz daisy chain parameters. sio timing (continued) 70 tssyncf ? (rxcr) sync fall to rxc rise setup ? (external sync mode) ?100 ?100 ?100 ns 71 tdcf(ieor) clock fall to ieo rise delay 90 75 60 ns 72 tdcf(ieof) clock fall to ieo fall delay 110 90 75 ns 73 thdi(m1r,rdr) data hold time to m1 rise or rd ? rise 000ns 74 tsm1/rd(c) setup time for m1 and rd to clock rising (with data valid) 20 20 20 ns figure 42. internal da isy chain configuration table 5. ac characteristics of the z84c90 (continued) no. symbol parameter 8 mhz 10 mhz 1,6 12.5 mhz 1,6 u/m min max min max min max notes: 1. maximum sio data rate is f clock by 5, in which f clock = 1 t c c. 2. for a z80 cpu operating above 8 mhz, one wait state is required to meet this parameter. 3. these daisy chain parameters include contributions fr om the pio, sio and ctc cells, and vary slightly depending on how they are ordere d by the kio command register. 4. counter mode only; when using a cycle time less than 3 tcc, parameter #37 must be met. 5. units are tcc. 6. if the cpu is a z80 cpu and if it is required to have mu ltiple z80 peripherals in the system, then the time period between m1 to iorq must be extended. 7. any open-drain output must add a re gister-capacitor (rc) time cons tant to the specification value. iei input buffer device #1 device #2 device #3 output buffer ieo
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 43 the data that support the calculations in table 6 are tabulated in table 7. table 6. daisy chain parameters no. symbol parameter 8 mhz 10 mhz 12.5 mhz unit min max min max min max 18 1 tdm1(ieo) (pio at #1) 160 150 125 ns (ctc at #1) 180 150 125 ns (sio at #1) 230 200 160 ns 19 2 tsiei (io) (pio at #3) 170 140 115 ns (ctc at #3) 170 160 135 ns (sio at #3) 180 160 130 ns 20 3 tdiei(ieof) 160 150 125 ns 21 4 tdiei(ieor) 160 150 125 ns notes: to calculate z80 kio daisy-chain timing, use the z80 pi o, ctc, and sio with i/o bu ffers on the chain. consider the following calculation formulas: 1. parameter 18: m1 falling to ieo delay tdm1(ieo) = td m1(ieo)#1 + tdiei(ieo)#2 + tdiei(ieo)#3 + output buffer delay), in which tdiei(ieo) refers to the wo rst-case number value between tdiei(ieor) and tdiei(ieof). 2. parameter 19: iei to iorq falling setup time tsiei(io) = tdiei(ieo)#1 + tdiei(ieo) #2 + tdiei(ieo)#3 + input buffer delay), in which tdiei(ieo) refers to the wo rst-case number value between tdiei(ieor) and tdiei(ieof). 3. parameter 20: iei falling delay = tdiei(ieof) = tdiei(ie of)pio + tdiei(ie of)ctc + tdiei(ieof)sio + (input buffer delay) + (output buffer delay). 4. parameter 21: iei rising to ieo rising delay (after ed decode) ? tdiei(ieor) = tdiei(ieor)pio + tdiei(ieor)ctc + tdiei(ieor)sio + ((input buffer delay) + (output buffer delay). 5. in notes 1?4, tdiei(ieo) refers to the worst-case number value between the parameters tdiei(ieor) and tdiei(ieof). table 7. daisy chain calculation data* 8 mhz 10 mhz 12.5 mhz unit min max min max min max input buffer delay 10 10 10 ns output buffer delay 10 10 10 ns 8 mhz pio part ctc part sio part ns tdm1(ieo) 60 80 120 ns tsiei(io) 70 70 70 ns tdiei(ieof) 50 50 40 ns tdiei(ieor) 50 50 40 ns note: *when using an interrupt from only a portion of the z84c90 kio, the numbers in this table are smaller than the actual values. for example, in figure 42 on page 42, if device #1 is pio, device #2 is ctc, and device #3 is sio, then at 12.5 mhz, parameter #18 in table 6, tdm1(ieo), is pio tdm1(ieo) + ctc tdiei(ieo) + sio (tdiei(ieo) + output buffer. = 50 ns + 40 ns + 25 ns + 10 ns = 125 ns.
ps011804-0612 ac characteristics z84c90 kio serial/parallel counter/timer product specification 44 10 mhz pio part ctc part sio part ns tdm1(ieo) 60 60 90 ns tsiei(io) 50 70 50 ns tdiei(ieof) 50 50 30 ns tdiei(ieor) 50 50 30 ns 12.5 mhz pio part ctc part sio part ns tdm1(ieo) 50 50 70 ns tsiei(io) 40 60 40 tdiei(ieof) 40 40 25 tdiei(ieor) 40 40 25 table 7. daisy chain calc ulation data* (continued) 8 mhz 10 mhz 12.5 mhz unit min max min max min max note: *when using an interrupt from only a portion of the z84c90 kio, the numbers in this table are smaller than the actual values. for example, in figure 42 on page 42, if device #1 is pio, device #2 is ctc, and device #3 is sio, then at 12.5 mhz, parameter #18 in table 6, tdm1(ieo), is pio tdm1(ieo) + ctc tdiei(ieo) + sio (tdiei(ieo) + output buffer. = 50 ns + 40 ns + 25 ns + 10 ns = 125 ns.
ps011804-0612 packaging z84c90 kio serial/parallel counter/timer product specification 45 packaging zilog?s z84c90 kio is availa ble in the following packages: ? 84-pin plastic chip carrier (plcc) ? 100-pin quad flat pack (lqfp) ? current diagrams for each of the se packages are published in zilog?s packaging product specification (ps0072) , which is available free for do wnload from the zilog website.
ps011804-0612 ordering information z84c90 kio serial/parallel counter/timer product specification 46 ordering information order your z84c90 kio serial/parallel counte r/timer products from zilog using the part numbers shown in table 8. for more informa tion about ordering, please consult your local zilog sales office. the sales location page on the zilog website lists all regional offices. part number su ffix designations zilog part numbers consist of a number of components, as indicated in the following example. example. part number z84c9008asg is an 8-bit z80-powered mcu operating at an 8 mhz frequency in a 100-pin lqfp package, operating within a 0o c to +70oc tempera- ture range and built us ing lead-free solder. table 8. z84c90 kio ordering matrix part number frequency package temperature range z84c9008asg 8 mhz 100-pin lqfp 0c to 70c Z84C9008VEG 8 mhz 84-pin plcc ?40c to +105c z84c9008vsg 8 mhz 84-pin plcc 0c to 70c z84c9010asg 10 mhz 100-pin lqfp 0c to 70c z84c9010veg 10 mhz 84-pin plcc ?40c to +105c z84c9010vsg 10 mhz 84-pin plcc 0c to 70c z84c9012vsg 12.5 mhz 84-pin plcc 0c to 70c z84 c 90 08 a s g environmental flow ? g = green plastic packaging compound temperature range s = standard, 0c to 70c ? package a = 100-pin lqfp speed 08 = 8 mhz frequency device type memory type ? c = cmos device family z80 = zilog?s 8-bit cpu
ps011804-0612 precautions & limitations z84c90 kio serial/parallel counter/timer product specification 47 precautions & limitations the following issues describe the possible limitations and resulting workarounds when working with revision a of the z84c90 kio peripheral. daisy-chain if the kio has an interrupt pending during an interrupt acknowle dge cycle, the kio misses the status of the ie1 pin. as a result, vector contention is produced if there is a higher interrupting device. howeve r, operation is as expected if only one device is in the system. workaround: there is no problem if the application has only one peripheral in the daisy chain. for two or more pe ripherals in the system, a hardware workaround circuit is required. please contact your local zilog re presentative to obtain more information. reset kio requires the m1 signal to exit from a reset state. if the m1 signal is not received, the kio cannot be programmed. this problem does not exist for users of the z80 cpu. workaround: if the cpu is other than a z80 cpu, an m1 signal is required to exit reset status. otherwise, the kio cannot be programmed. port c when port c is used as a parallel i/o (and not as modem signals for an sio ) and there is a status change on pc1 or pc6, the status of synca or syncb (sio cell) also changes. workaround: before using port c as a parallel port, set the sio modem signal mode back to port c. this procedure avoids the problem. interrupt acknowledge cycle the kio modifies the contents of the kio control register (specifically, the kio modi- fies the daisy-chain configuration) if the ce pin is active during the interrupt acknowl- edge cycle (assuming othe r conditions are satisfied). this problem can occur under the following narrowly-defined conditions: ? the ce signal is active throughout th e interrupt acknowledge cycle ? the address on the bus, a3?a0, is 110b ? bit d3 is 1
ps011804-0612 precautions & limitations z84c90 kio serial/parallel counter/timer product specification 48 ? at the end of the interrupt acknowledge cycle, m1 goes inactiv e prior to the iorq signal ? during the time period in which c e is active, iorq is active, and m1 returns to the inactive state, all of which occur du ring the rising edge of the clock. ? this problem does not exist with the z80 cpu; however, other cpus could be affected. one of the possible workarounds is to add the m 1 not active condition to generate a ce signal.
ps011804-0612 customer support z84c90 kio serial/parallel counter/timer product specification 49 customer support to share comments, get your technical questio ns answered, or report issues you may be experiencing with our products, please vi sit zilog?s technical support page at ? http://support.zilog.com . to learn more about this product, find additional documentation, or to discover other fac- ets about zilog product offerings, please visit the zilog knowledge base at http:// zilog.com/kb or consider participating in the zilog forum at http://zilog.com/forum . this publication is subject to replacement by a later edition. to determine whether a later edition exists, please vis it the zilog website at http://www.zilog.com .

▲Up To Search▲

Price & Availability of Z84C9008VEG

	To Download Z84C9008VEG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .